In electronic circuits, overvoltages due to electrostatic discharge (ESD) can occur, by which the components of the circuit are destroyed. Electronic circuits are therefore often provided with ESD protection devices.
U.S. Pat. No. 5,751,042 A describes an ESD protection circuit for two mutually adjacent n-channel components with n+ regions for source and drain. The drain n+ region of the first n-channel component is connected to a positive terminal of a supply voltage, and the source n+ region of the second n-channel component is connected to a negative terminal of the supply voltage. The drain n+ region of the first n-channel component is arranged a distance away from the source of the n+ region of the second n-channel component and is isolated by a field oxide region. An n-type well, which increases the breakdown voltage at the pn junction, substantially overlaps the drain n+ region of the first n-channel component and extends up to the source n+ region of the second n-channel component. The well extends deeper into the substrate than the n+ regions and has a lower dopant concentration than the n+ regions.
As another possibility, this publication indicates the arrangement of a p+-type guard ring between the drain n+ region of the first n-channel component and the source n+ region of the second n-channel component. This is intended to reduce the current gain of the parasitic npn-bipolar transistor formed between the two n-channel components and thus prevent a so-called snap-back triggered by an electrostatic discharge.